混合信号数字ip设计工程师

Responsibilities

• Work with analog designer and system architecture to define the digital part for MSIP/ sub-system, including the functionality and algorithm.

• Implement RTL design with high quality in gate count reduction, DFT coverage and timing closure.

• Implement digital part verification and IP level mixed signal verification;

• Work with analog designer Ｏn MSIP view generation and documentation delivery;

• Support SoC level integration / verification / silicon validation

Requirements

• Master degree in micro-electronics, electronic engineering or relevant disciplines.

• Good knowledge in Verilog, VHDL, System Verilog, System C or E, and script language.

• Familiar with Unix/Linux system and EDA tool from Cadence, Synopsis, Mentor for digital and analog development.

• Experience with Ｏne or more of the following is a plus: power management, 8bit, 16bit or 32bit Micro-controller, ARM or AHB bus system, script languages.

• Basic knowledge of analog and mix-signal design and simulation is a plus.

• Good communication skills and teamwork for global projects support;