soc dft engineer可测性设计

DFT Job Description:

As part of the SOC design team, engineer will mainly focus Ｏn following areas, but not limited to:

1. Block, IP and SoC level DFT implementation including: RTL coding integration, MBIST insertion/verification, Boundary scan insertion/verification, Scan insertion & compression, Ｏn chip clocking for at-speed test, analog/hard IP test.

2. Block level spyglass DFT DRC check & fix it in RTL/Netlist level;

3. Block level DFT constraint generation, scan insertion and formal check;

4. Test patterns/vectors generation and verification, Silicon debug and yield improvement.

Job Requirement 

1. Hand Ｏn experience of block level and SoC DFT implementation. Scan Compression logic/MBIST logic/Boundary scan chain insertion, pattern bring up and diagnosis；

2. Expertise with Mentor/Synopsys DFT tools;

3. Experience in MBIST/SCAN/ATPG Pattern simulation and debug Ｏn RTL & Netlist；

4. A high-level of self-motivation and a proactive approach to solving problems.