数字设计工程师（STA）

JOB DEscriptION:
1. Build SoC/IP level Spyglass/Synthesis/Timing Analysis/Formality Check/CDC flow
2. Do SoC/IP level synthesis / timing analysis / formality check / CDC check
3. Deliver constraints and closely co-work timing closure with P&R
4. Take some block level RTL coding

QUALIFICATION:
1. MSEE with ＞3 year experience of digital design experience;
2. Relevant experience in complex timing closure;
3. Be familiar with DC/PT/formality check tools
4. Be familiar with Tcl/Perl/…. scripts language
5. RTL coding experience is a plus