资深逻辑验证工程师/验证部门经理

工作职责

1.   Understand the expected functionality of designs;

2.   Design and develop verification environment; 

3.   Run RTL and gate-level simulations/regression;

4.   Code/functional coverage development, analysis and closure;

5.   Release the documents during the verification flow, such as verification plan, usage of the verification environment, simulation result of test cases, verification coverage report, etc.

职位要求

1.   Minimum of 5 years design/verification experience (test plan, test bench, assertions, debugging designs, code coverage etc.);

2.   Familiar with design and verification languages (Verilog, System Verilog, SVA etc.);

3.   script and automation skills (tcl, perl, makefile etc) a plus;

4.   Additional qualifications include: Good IC verification skills and basic knowledge of logic or circuit design;

5.   Independent and self-management;

6.   Cooperative and proactive in daily work.