岗位职责:
1、RTL/Digital circuit design, synthesis, and simulation/verification;
2、FPGA synthesis, verification;
3、Generate test pattern;
4、Frontend Design Flow;
5、Familiar with ASIC implementation/sign-off flow, including synthesis, testing, ATPG/BIST design。
任职资格:
1、8年以上相关经验;
2、学历要求硕士以上。
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