职责描述:
Responsible for entire analog transistor level circuit design;
Physical layout design;
Architecture design for senior level positions;
任职要求:
MS or PhD in Electrical Engineering preferred;
MS degree with 3+ years of CMOS transistor level analog design;
PhD with 2+ years of CMOS transistor level analog design experience;
Experience with device evaluation and debugging is required;
Familiarity with high-speed SerDes PHY design is a plus but not required;
Prior automotive IC design experience is a plus.
Copyright C 2003~2023 All Rights Reserved 版权所有 eetop 京ICP备2021015159号-1
地址:北京市朝阳区将台路5号院1号楼2层2010室 EMAIL:wangtingting@eetop.com.cn
Powered by PHPYun.